subdevices
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| subdevices [2023/12/19 12:55] – [ADC] ursgraf | subdevices [2024/04/09 20:46] (current) – [DAC] ursgraf | ||
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| Line 49: | Line 49: | ||
| |0x28|4|value_1|r/ | |0x28|4|value_1|r/ | ||
| |..|4|..|r/ | |..|4|..|r/ | ||
| - | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses a pin on the FPGA device for each channel. | + | The status register in the subheader is unused with this function. In the configuration register setting the bit 0 will reset the subdevice. This subdevice uses 5 pins. |
| ==== Subtypes ==== | ==== Subtypes ==== | ||
| Currently there is one subtype of this subdevice. The subtype information can be found in the '' | Currently there is one subtype of this subdevice. The subtype information can be found in the '' | ||
| ^Subtype ID^Description^Example^ | ^Subtype ID^Description^Example^ | ||
| |0x1|Simple DAC where the outputs are continuously set. All channels are updated at the same time|AD5668| | |0x1|Simple DAC where the outputs are continuously set. All channels are updated at the same time|AD5668| | ||
| + | |0x2|Simple DAC where the outputs are continuously set. All channels are individually updated, +-10V|AD5754| | ||
| ===== GPIO ===== | ===== GPIO ===== | ||
subdevices.1702986948.txt.gz · Last modified: 2023/12/19 12:55 by ursgraf
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